The Saturday tutorial sessions on emerging technologies have become a popular part of the IEDM conference. They are presented by experts in the field to bridge the gap between textbook-level knowledge and leading-edge current research, and to introduce attendees to new fields of interest. This year there will be three time slots, each with two tutorials running in parallel:

1:30 PM - 2:50 PM PST

Tut-1 Advances in CMOS Technologies and Cell Height Scaling Considerations | Yanbin Luo, Intel

Tut-2 Neuromorphic Computing

3:05 PM - 4:25 PM PST

Tut-3 Atomic-Layer-Deposited Atomically Thin In2O3 Transistors for BEOL Logic and Memory Applications | Peide Ye, Purdue University

Tut-4 Quantum Computing – Concepts, Status Quo and Challenges Ahead | Hendrik Bluhm, RWTH Aachen University, Forschungszentrum Jülich, ARQUE Systems GmbH

4:40 PM - 6:00 PM PST

Tut-5 Developing a Reliable and Open Chiplet Eco-System for Wafer-Scale Systems | Subramanian S. Iyer, UCLA

Tut-6 High-Speed Memory Solutions for ML and High-Performance Compute | Yih Wang, TSMC

9:00 AM - 6:00 PM

IEEE IEDM will offer two in-depth short courses led by world-renowned experts, focusing on highly relevant and timely topics.

Short Course 1: Advanced Logic and System Technologies in the AI Era

Organizer - Tenko Yamashita | IBM

This course features six sessions covering:

• SC 1.1 Device Technologies for GAA Scaling and Emerging Alternatives | Myunggil Kang, Samsung Electronics

• SC 1.2 Advanced Interconnects Technologies for Cu Extension and Beyond | Koichi Motoyama, IBM

• SC 1.3 Process Innovations and Materials to Sustain Moore’s Law in the Era of GAA and CFET | Nicolas Breil, AMAT

• SC 1.4 Silicon Photonics for High-Speed, Energy-Efficient Data Transfer | Di Liang, University of Michigan

• SC 1.5 Advanced Packaging and Chiplet Technologies for AI and HPC | James Chen, TSMC

• SC 1.6 System Technology Co-Optimization (STCO) for Thermal Management and Power Delivery in Heterogeneous Integration | Kenneth Larson, Synopsis

Short Course 2: Advanced Memory Technologies for Energy-Efficient AI and HPC

Organizer - Duygu Kuzum, UC San Diego

This course includes six sessions exploring:

• SC 2.1 Memory-Centric AI Architectures Via Advanced Packaging and Heterogeneous Integration | Nuwan Jayasena, AMD

• SC 2.2 Big AI for Small Devices | Hai Li, Duke University

• SC 2.3 Exploring the Evolution of DRAM Technology: Operation Principles, Scaling Challenges, and the Emergence of HBM | Daehyun Moon, Samsung Electronics

• SC 2.4 High-Density 3D Flash Memory in the CMOS Directly Bonded to Array (CBA) Era and Beyond | Katsuyuki Sekine, Kioxia

• SC 2.5 Process and Material Innovations for Memory Scaling | Noboru Ooike, TEL

• SC 2.6 Emerging Memory Technologies for Next-Generation AI and HPC Applications | Fabio Pellizzer, Micron

9:00 AM - 12:15 PM Keynote

• Hillery Hunter, CTO, IBM Infrastructure and GM, Innovation; IBM Fellow at IBM

• PR “Chidi” Chidambaram, Senior Vice President & Fellow at Qualcomm

1:30 PM - 5:20 PM Technical Sessions

6:30 PM - 8:00 PM Monday Evening Reception

9:00 AM - 12: 30 PM Technical Sessions
12:20 PM - 2:00 PM Tuesday Lunch
2:15 PM - 6:05 PM Technical Sessions
8:00 PM - 10:00 PM Evening Panel

9:00 AM - 12:30 PM Technical Sessions
1:30 PM - 5:20 PM Technical Sessions